Proceedings Design, Automation and Test in Europe

The following topics were covered: design optimization of building blocks; HW/SW partitioning and communication synthesis; asynchronous and hybrid VHDL-based design; data path and FPGA testing; design methods for high performance applications; scheduling in embedded systems; advanced techniques for VHDL design; BIST approaches; image processing architectures; scheduling and analysis of HW/SW systems; extensions to VHDL; error detection and design validation; IP-based system-on-a-chip design; design reuse methodologies; flat and timing driven processor design; reconfigurable systems; digital simulation and estimation; synthesis of reprogrammable and reconfigurable architectures; partitioning and routing; formal verification; simulation for high-level design; architectural synthesis; timing and crosstalk in interconnect; IDDQ and memory testing; microsystems; interconnect modelling; design for manufacturability; sequential circuit testing; behavioural synthesis; formal equivalence checking using decision diagrams; silicon debug of systems-on-chips; characterization and verification of analogue circuits; benchmark circuits, technology mapping and scan chains; physical to gate level design for low power; embedded memory and logic; combinational logical synthesis; high level power estimation; Petri nets and dedicated formalisms; mixed-signal test and DFT; sequential logic synthesis; high-level power optimisation; system architecture design; simulation and test tools for analogue circuits