DocumentCode :
2643504
Title :
Optimization and modeling of FPGA implementation of the Katan Cipher
Author :
Mohd, Bassam Jamil ; Hayajneh, Thaier ; Abu Khalaf, Zaid
Author_Institution :
Comput. Eng. Dept., Hashemite Univ., Zarqa, Jordan
fYear :
2015
fDate :
7-9 April 2015
Firstpage :
68
Lastpage :
72
Abstract :
Lightweight ciphers (e.g., Katan) are crucial for secure communication for resource-constrained devices. The Katan cipher algorithm was proposed for low-resource devices. This paper examines implementing Katan Cipher on field programmable gate array (FPGA) platform. The paper discusses several implementations, with 80-bits key size and 64-bits block size. The energy and power dissipations are examined to select the optimum design. Models for resources and power are derived with average error of 12% and 17%.
Keywords :
circuit optimisation; cryptography; field programmable gate arrays; telecommunication security; FPGA implementation; Katan cipher algorithm; energy dissipation; field programmable gate array; power dissipation; resource-constrained devices; secure communication; Algorithm design and analysis; Ciphers; Encryption; Field programmable gate arrays; Hardware; Timing; Cipher; Encryption; Energy; FPGA; Power; Security;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information and Communication Systems (ICICS), 2015 6th International Conference on
Conference_Location :
Amman
Type :
conf
DOI :
10.1109/IACS.2015.7103204
Filename :
7103204
Link To Document :
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