DocumentCode :
2643587
Title :
Yield-aware Placement Optimization
Author :
Azzoni, P. ; Bertoletti, M. ; Dragone, N. ; Fummi, F. ; Guardiani, C. ; Vendraminetto, W.
Author_Institution :
Verona Univ.
fYear :
2007
fDate :
16-20 April 2007
Firstpage :
1
Lastpage :
6
Abstract :
In this paper we describe a methodology addressing the issue of avoiding yield hazardous cell abutments during placement. This is made possible by accurate characterization of the yield penalty associated with particular cell-to-cell interactions. Of course characterizing all possible cell abutments in a library of 600+ cells is impractical. We will describe some simple heuristics that attempt to resolve the cell abutment pre-characterization complexity. Finally we will show a possible implementation of the proposed yield-aware placement optimization methodology and demonstrate the potential of cell interaction penalty characterization for a 90nm design test case
Keywords :
integrated circuit design; integrated circuit yield; optimisation; 90 nm; cell interaction penalty characterization; cell-to-cell interactions; yield hazardous cell abutments; yield penalty; yield-aware placement optimization; Constraint optimization; Cost function; Design for manufacture; Design optimization; Integrated circuit interconnections; Integrated circuit modeling; Lithography; Optimization methods; Testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
Type :
conf
DOI :
10.1109/DATE.2007.364464
Filename :
4211974
Link To Document :
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