Hierarchy-a CHDStd tool for the coming deep submicron complex design crisis

Author

Grout, S. ; Ledenbach, G. ; Bushroe, R.G. ; Fisher, P. ; Cottrell, D. ; Mallis, D. ; DasGupta, S. ; Morrell, J. ; Sayah, J. ; Gupta, R. ; Patel, PT ; Adams, P.

Author_Institution

Sematech, Austin, TX, USA

fYear

1998

fDate

10-13 Feb 1998

Firstpage

257

Lastpage

260

Abstract

This paper describes the use of a hierarchical design representation standard, CHDStd, as part of the architecture of the Chip Hierarchical Design System (CHDS). Details are given on CHDStd-based hierarchy mechanisms and processes required to support Forward Timing-Driven Hierarchical Design capabilities needed for chip design using 0.25u-0.18u technologies and beyond. These capabilities solve some of the key challenges identified by the semiconductor industry´s Design Productivity Crisis. This paper identifies the role of hierarchy for handling difficult chip design information issues and for large complex chip design

Keywords

circuit layout CAD; integrated circuit design; CHDStd tool; Chip Hierarchical Design System; Hierarchy; hierarchical design representation standard; large complex chip design; Chip scale packaging; Collision mitigation; Conductors; Electronic design automation and methodology; Process design; Productivity; Silicon; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-4425-1

Type

conf

DOI

10.1109/ASPDAC.1998.669460

Filename

669460