Computing Synchronizer Failure Probabilities

System-on-chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchronizers must be characterized accurately to ensure the robustness of the complete system. We present a novel approach for determining the failure probabilities of synchronizer circuits. Our approach use numerical integration to account for the nonlinear behaviour of real synchronizer circuits. We complement this with small-signal techniques to enable accurate estimation of extremely small failure probabilities. Our approach is fully automated, is suitable for integration into circuit simulation tools such as SPICE and enables accurate characterization of extremely small failure probabilities