RAM-based FPGAs: a test approach for the configurable logic

Author

Renovell, M. ; Portal, J.M. ; Figueras, J. ; Zorian, Y.

Author_Institution

LIRMM-UM, Montpellier, France

fYear

1998

fDate

23-26 Feb 1998

Firstpage

82

Lastpage

88

Abstract

This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic test configurations to fully test the whole matrix of CLBs. In the proposed test configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of test configurations 8 is fixed and independent of the FPGA size

Keywords

controllability; field programmable gate arrays; integrated circuit testing; logic testing; observability; random-access storage; C-testability property; RAM-based FPGA; XILINX 4000 family; configurable logic; one-dimensional iterative arrays; test configurations; Application specific integrated circuits; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic devices; Logic testing; Manufacturing; Programmable logic arrays; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 1998., Proceedings

Conference_Location

Paris

Print_ISBN

0-8186-8359-7

Type

conf

DOI

10.1109/DATE.1998.655840

Filename

655840