Behavioral Modeling of Delay-Locked Loops and its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems

Author

Barajas, E. ; Cosculluela, R. ; Coutinho, D. ; Mateo, D. ; González, J.L. ; Cairó, I. ; Banda, S. ; Ikeda, M.

Author_Institution

Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona

fYear

2007

fDate

16-20 April 2007

Firstpage

1

Lastpage

6

Abstract

This paper presents a behavioral model of a delay-locked loop (DLL) used to generate the timing signals in an integrated ultra wide-band (UWB) impulse radio (IR) system. The requirements of these timing signals in the context of UWB-IR systems are reviewed. The behavioral model includes a modeling of the various noise sources in the DLL that produce output jitter. The model is used to find the optimum loop filter capacitor value that minimizes output jitter. The accuracy of the behavioral model is validated by comparing the system level simulation results with transistor level simulations of the whole DLL

Keywords

delay lock loops; integrated circuit modelling; jitter; timing circuits; ultra wideband communication; behavioral modeling; delay-locked loops; jitter optimization; optimum loop filter capacitor value; system level simulation; timing signals; transistor level simulation; ultra wideband impulse radio systems; Degradation; Delay; Jitter; Matched filters; Pulse modulation; Research and development; Signal generators; Space vector pulse width modulation; Timing; Ultra wideband technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07

Conference_Location

Nice

Print_ISBN

978-3-9810801-2-4

Type

conf

DOI

10.1109/DATE.2007.364499

Filename

4212009