Title :
28nm FDSOI technology platform for high-speed low-voltage digital applications
Author :
Planes, N. ; Weber, O. ; Barral, V. ; Haendler, S. ; Noblet, D. ; Croain, D. ; Bocat, M. ; Sassoulas, P. -O ; Federspiel, X. ; Cros, A. ; Bajolet, A. ; Richard, E. ; Dumont, B. ; Perreau, P. ; Petit, D. ; Golanski, D. ; Fenouillet-Béranger, C. ; Guillot,
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.
Keywords :
SRAM chips; buried layers; field effect memory circuits; silicon-on-insulator; FDSOI technology platform; SRAM array; SRAM cells; fully depleted SOI technology; high speed low voltage digital applications; memory access time; size 28 nm; voltage 0.6 V; voltage 1 V; Complexity theory; Delay; Logic gates; MOS devices; Random access memory; Standards; Very large scale integration;
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
DOI :
10.1109/VLSIT.2012.6242497
