Title :
A flat, timing-driven design system for a high-performance CMOS processor chipset
Author :
Koehl, Juergen ; Baur, Ulrich ; Ludwig, Thomas ; Kick, Bernhard ; Pflueger, Thomas
Author_Institution :
IBM Entwicklung GmbH, Boeblingen, Germany
Abstract :
We describe the methodology used for the design of the CMOS processor chipset used in the IBM S/390 Parallel Enterprise Server-Generation 3. The majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. The result is a globally optimized solution without artificial floorplan boundaries. We show that the density in terms of transistors per mm2 is comparable to the most advanced custom designs and that the impact of interconnect delay on the cycle time is very small. Compared to custom design, this approach offers excellent turn-around-time and considerably reduces overall effort
Keywords :
CMOS digital integrated circuits; VLSI; circuit layout CAD; circuit optimisation; high level synthesis; integrated circuit design; integrated circuit layout; microprocessor chips; storage management chips; timing; timing circuits; CAD; IBM S/390 Parallel Enterprise Server; cycle time; flat timing-driven design system; floorplan; globally optimized solution; high-performance CMOS processor chipset; interconnect delay; standard cell elements; Algorithm design and analysis; CMOS logic circuits; CMOS process; Circuit synthesis; Circuit testing; Design optimization; Logic arrays; Timing; Transistors; Virtual manufacturing;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655874
