DocumentCode
2646046
Title
Reduced Hamming count and its aliasing probability
Author
Gleason, Anita ; Jone, Wen-Ben
Author_Institution
Dept. of Comput. Sci., New Mexico Polytech., Socorro, NM, USA
fYear
1991
fDate
14-16 Oct 1991
Firstpage
356
Lastpage
359
Abstract
Hardware overhead reduction through counter selection is considered for the Hamming count compaction test. A method to choose the most effective syndrome and input variable counter pair is given. Both simulation and theoretical analysis illustrate that this method produces an optimal pairing. The aliasing probability of this two-counter test is developed and shown to reduce the exhaustive ones count aliasing probability by half an order
Keywords
logic testing; aliasing probability; compaction test; counter selection; hardware overhead reduction; optimal pairing; reduced Hamming count; simulation; two-counter test; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Computer science; Counting circuits; Fault detection; Hardware; Probability;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-2270-9
Type
conf
DOI
10.1109/ICCD.1991.139918
Filename
139918
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