DocumentCode :
2646619
Title :
Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking
Author :
Ghosh, Debabrata ; Kapur, Nevin ; Harlow, Justin, III ; Brglez, Franc
Author_Institution :
Lab. of Collaborative Benchmarking, North Carolina State Univ., Raleigh, NC, USA
fYear :
1998
fDate :
23-26 Feb 1998
Firstpage :
656
Lastpage :
663
Abstract :
This paper formalizes the synthesis process of wiring signature-invariant (WSI) combinational circuit mutants. The signature σ0 is defined by a reference circuit η0, which itself is modeled as a canonical form of a directed bipartite graph. A wiring perturbation γ induces a perturbed reference circuit ηγ. A number of mutant circuits ηγi can be resynthesized from the perturbed circuit ηγ. The mutants of interest are the ones that belong to the wiring-signature-invariant equivalence class Nσ0, i.e. the mutants ηγi∈N σ0. Circuit mutants ηγi∈Nσ0 have a number of useful properties. For any wiring perturbation γ, the size of the wiring-signature-invariant equivalence class is huge. Notably, circuits in this class are not random, although for unbiased testing and benchmarking purposes, mutant selections from this class are typically random. For each reference circuit, we synthesized eight equivalence subclasses of circuit mutants, based on 0 to 100% perturbation. Each subclass contains 100 randomly chosen mutant circuits, each listed in a different random order. The 14,400 benchmarking experiments with 3200 mutants in 4 equivalence classes, covering 13 typical EDA algorithms, demonstrate that an unbiased random selection of such circuits can lead to statistically meaningful differentiation and improvements of existing and new algorithms
Keywords :
circuit CAD; circuit layout CAD; combinational circuits; design of experiments; directed graphs; equivalence classes; logic CAD; EDA algorithms; benchmarking applications; canonical form; combinational circuit mutants; directed bipartite graph; reference circuit; synthesis process; wiring perturbation; wiring signature-invariant circuit mutants; wiring-signature-invariant equivalence class; Algorithm design and analysis; Benchmark testing; Bipartite graph; Circuit synthesis; Circuit testing; Combinational circuits; Electronic design automation and methodology; Pins; Very large scale integration; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
Type :
conf
DOI :
10.1109/DATE.1998.655928
Filename :
655928
Link To Document :
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