Title :
A verified platform for a gate-level electronic control unit
Author :
Tverdyshev, Sergey
Author_Institution :
Dept. of Comput. Sci., Saarland Univ., Saarbrucken, Germany
Abstract :
We present the formal integration of an automotive bus controller into a formally verified gate-level computer system. This system consists of a complex processor and generic devices which run in parallel. The system specification is an instruction set architecture with concurrently running visible devices. The built system is an electronic control unit which is the base element for a distributed automotive system and its size on an FPGA is ca. 5 M gate equivalents.
Keywords :
controllers; distributed processing; field programmable gate arrays; formal verification; instruction sets; reduced instruction set computing; 32-bit RISC processor; C VAMP processor; FPGA; automotive bus controller; complex processor; distributed automotive system; formal integration; formally verified gate-level computer system; gate-level electronic control unit; generic devices; instruction set architecture; pipelined processor; Assembly systems; Automotive engineering; Computer architecture; Control systems; Field programmable gate arrays; Hardware; Instruction sets; Operating systems; Real time systems; Utility programs;
Conference_Titel :
Formal Methods in Computer-Aided Design, 2009. FMCAD 2009
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4966-8
Electronic_ISBN :
978-1-4244-4966-8
DOI :
10.1109/FMCAD.2009.5351125
