Realization of OFDM Modulator and Demodulator for DSRC Vehicular Communication System Using FPGA Chip

Following the DSRC vehicular communications IEEE802.11p physical layer standards, this paper presents the required computing time estimations of baseband processing modules on the DSP platform and uses this estimation to explain the decision of choosing to implement the 64 point IFFT/FFT module with the FPGA chip. The IFFT/FFT processing time of OFDM modulator/demodulator circuits in applications of DSRC vehicular communication system transceivers must be less than the symbol interval of 8 musec in order to satisfy the requirement of real-time DSRC communications. The 64-IFFT/FFT processing module presented in this paper uses a parallel processing structure of four butterfly circuit units, is capable of processing 16-bit digital signals, and completes 64-IFFT/FFT calculations in 5.33 musec (< 8 musec) with a 24 MHz FPGA chip. Ten short training symbols of the DSRC system are sent through the FPGA IFFT/FFT module to verify its functionality and performance