Title :
Power noise analysis acceleration technique by linear programming
Author :
Suzuki, Goro ; Gomakubo, Takeshi
Author_Institution :
Univ. of Kitakyushu, Fukuoka, Japan
Abstract :
In the early floor plan, power noise DC analysis by linear programming method has been proposed [1]. In order to accelerate the analysis speed, we propose new objective functions and also new constraints for linear programming. Using our new ideas can accelerate analysis speed by about 105 times, comparing with conventional method in the case of 20 horizontal x 20 vertical power nets noise analysis for 19 application program execution cycles.
Keywords :
error analysis; integrated circuit layout; integrated circuit noise; linear programming; floor plan; linear programming; power noise analysis acceleration technique; Acceleration; Circuit analysis; Circuit noise; Equations; Kirchhoff´s Law; Linear programming; Noise reduction; Short circuit currents; Vectors; Voltage; Early floor plan; Linear programming; Power noise analysis;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351203
