DocumentCode :
26495
Title :
Improving Equipment Defectivity Specifications Through Chip Yield Modeling: A Case Study for Immersion Lithography
Author :
Boogaard, Arjen ; Smith, I. ; Mouraille, Orion ; Knaapen, Thijs ; Stegen, Raf
Author_Institution :
ASML, Veldhoven, Netherlands
Volume :
26
Issue :
3
fYear :
2013
fDate :
Aug. 2013
Firstpage :
423
Lastpage :
429
Abstract :
Semiconductor equipment suppliers are asked to build tools that can operate almost continuously. Once such a reliable tool is developed, defect data collection, understanding, and reduction become increasingly important since the tool has to manufacture reliable (layers of) semiconductor devices that scarcely fail. At this stage, semiconductor equipment suppliers could benefit from the concepts of chip yield modeling, because it directly relates their defect data to the yield of semiconductor devices. We present a case study in which we estimate the yield impact of defects related to immersion photolithography scanners. Defects were separated into various classes, and the size distributions of those classes were measured. Given a circuit´s critical area, forecasting of the yield for any defect class becomes straightforward, and also yield predictions can be made for future technology nodes, resulting in the optimal choice of yield-enhancing strategies.
Keywords :
immersion lithography; semiconductor device reliability; build tools; chip yield modeling; data collection; equipment defectivity specifications; immersion lithography; semiconductor equipment suppliers; yield-enhancing strategies; Critical area; defect size distribution; defect–yield correlation; immersion lithography; yield estimation;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2013.2258693
Filename :
6504539
Link To Document :
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