Title :
Distributed diagnosis for wafer scale systems
Author_Institution :
Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Abstract :
The increasing demand for high performance systems has led to the design of systems comprised of a large number of processing elements on a single wafer. This paper presents a distributed diagnosis algorithm for wafer scale systems. Unlike other approaches, the algorithm does not assume diagnostic circuits are fault-free. The algorithm is simple enough to be realized with small circuit overhead. Computer simulation has shown that even for low unit yields, extremely high performance (fault coverage) can be achieved by properly tuning the algorithm parameters
Keywords :
VLSI; fault tolerant computing; integrated circuit technology; microprocessor chips; parallel architectures; distributed diagnosis algorithm; fault coverage; small circuit overhead; wafer scale systems; Algorithm design and analysis; Circuit faults; Circuit optimization; Computer architecture; Computer science; Computer simulation; Distributed algorithms; Fault diagnosis; System testing; Voting;
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
DOI :
10.1109/ICWSI.1990.63900