DocumentCode
2650145
Title
An on-chip test scheme for SRAMs
Author
Lala, P.K. ; Walker, A.
Author_Institution
Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
fYear
1994
fDate
8-9 Aug 1994
Firstpage
16
Lastpage
20
Abstract
Semiconductor technology continues to progress dramatically. With the increasing density, the testing of RAM chips has become progressively more difficult. In this paper, a new approach to simplify the testing of large SRAMs (static RAMs), embedded in VLSI chips or as stand-alone chips, by incorporating additional circuitry is proposed
Keywords
SRAM chips; VLSI; built-in self test; fault diagnosis; integrated circuit testing; IC testing; SRAMs; VLSI chips; on-chip test scheme; stand-alone chips; static RAMs; Automatic testing; Circuit faults; Circuit testing; Compaction; Decoding; Logic arrays; Logic testing; Random access memory; Read-write memory; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-6245-X
Type
conf
DOI
10.1109/MTDT.1994.397203
Filename
397203
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