Title :
Low-area 1-kb multi-bit OTP IP design
Author :
Jin, Li-Yan ; Kim, Tae-Hoon ; Lee, Cheon-Hyo ; Ha, Pan-Bong ; Kim, Yong-Hee
Author_Institution :
Dept. of Electron. Eng., Changwon Nat. Univ., Changwon, South Korea
Abstract :
In this paper 1-kb multi-bit OTP IP, which is non-volatile memory, is designed for a power management IC. A conventional multi-bit OTP cell uses isolated NMOS transistor, but the cell size is large in the BCD process. So, PMOS transistor is used instead of the isolated NMOS transistor as antifuse, and the cell size is minimized by optimizing the size of PMOS transistor. In addition, an ESD protection circuit is added to prevent the case that any cell is programmed by high voltage at ESD test. The 1kb OTP IP is designed using Dongbu´s 0.18¿m BCD process and the layout size of the IP is 160.490 × 506.255 ¿m 21.
Keywords :
BiCMOS memory circuits; MOSFET; electrostatic discharge; integrated circuit layout; random-access storage; BCD process; BiCMOS-DMOS process; ESD protection circuit; PMOS transistor; antifuse; isolated NMOS transistor; layout size; multi-bit OTP IP; nonvolatile memory; Analog integrated circuits; CMOS analog integrated circuits; Circuit testing; Electrostatic discharge; Energy management; MOS devices; MOSFETs; Nonvolatile memory; Protection; Voltage; ESD protection; Multi-bit OTP; PMOS antifuse; breakdown; thin gate oxide;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351324
