Title :
A circuit failure prediction mechanism (DART) for high field reliability
Author :
Sato, Yasuo ; Kajihara, Seiji ; Miura, Yukiya ; Yoneda, Tomokazu ; Ohtake, Satoshi ; Inoue, Michiko ; Fujiwara, Hideo
Author_Institution :
Kyusyu Inst. of Technol., Iizuka, Japan
Abstract :
This paper presents a novel circuit failure prediction mechanism for high field reliability. On-line testing at a power-on/off time of a system detects the circuits´ delay degradation that is caused by aging. Dedicated test vectors are applied using BIST architecture. Embedded ring oscillators are utilized to compensate the measured delay values for temperature or voltage shift. The concept and necessary conditions for the mechanism are introduced and some preliminary experimental results show the possible effectiveness of the approach.
Keywords :
built-in self test; delays; integrated circuit reliability; integrated circuit testing; oscillators; BIST architecture; circuit delay degradation; circuit failure prediction mechanism; dedicated test vectors; embedded ring oscillators; high field reliability; on-line testing; ubiquitous VLSI; voltage shift; Aging; Built-in self-test; Circuit testing; Degradation; Delay effects; Power system reliability; Ring oscillators; System testing; Temperature; Voltage-controlled oscillators; aging; delay degradation; failure prediction; on-line testing; power-off test; power-on test; ring oscillator;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351352
