Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs

Author

Tabkhi, Hamed ; Bushey, Robert ; Schirner, Gunar

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

Volume

6

Issue

4

fYear

2014

fDate

Dec. 2014

Firstpage

65

Lastpage

68

Abstract

This letter introduces function-level processors (FLPs) to fill the flexibility/efficiency gap between instruction-level processors (ILPs) and hardware accelerators (HWACCs). Compared to an ILP, an FLP has a coarser programmability at function-level constructed out of configurable function blocks (FBs) implementing market-oriented functions. FBs are connected via a MUX-based programmable interconnect, tuned for envisioned application flows, for realizing flexible macro pipelines. We demonstrate FLP benefits with an industry example of the pipeline-vision processor (PVP). Mapping six embedded vision applications, the PVP offers up to 22.4 GOPs/s with average power of 120 mW; consuming 17x and 6x less power than compared ILP and ILP + HWACCs approaches.

Keywords

multiprocessing systems; performance evaluation; pipeline processing; power aware computing; system-on-chip; FLP; HWACC; ILP; MUX; PVP; coarser programmability; flexibility-efficiency gap; function-level processor; hardware accelerators; instruction-level processors; low power architecture; market-oriented MPSoC; market-oriented functions; multiprocessor system-on-chips; pipeline-vision processor; Computer architecture; Functional programming; Multiprocessing systems; Power demand; Program processors; Programming; System-on-chip; Flexibility/efficiency trade-off; function-set architecture (fsa); heterogeneous architectures;

fLanguage

English

Journal_Title

Embedded Systems Letters, IEEE

Publisher

ieee

ISSN

1943-0663

Type

jour

DOI

10.1109/LES.2014.2327114

Filename

6823166