Title :
Innovative system-level design environment based on FORM for transport processing system
Author :
Higuchi, Kazushige ; Shirakawa, Kazuhiro
Author_Institution :
NTT Opt. Network Syst. Lab., Kanagawa, Japan
Abstract :
This paper presents a system-level design environment for data transport processing systems. In this environment, designers can easily verify system behavior by formally defining data structures and their related actions, without considering detailed timing. In addition, the verified specification can be translated into synthesizable RTL descriptions by a dedicated RTL generator. Thus, using lower-level EDA tools, actual hardware can be obtained directly from a system-level specification
Keywords :
circuit CAD; data handling; data structures; high level synthesis; multimedia communication; telecommunication computing; telecommunication terminals; ATM-AAL5 termination circuit design; FORM; data structures; data transport processing systems; dedicated RTL generator; frame oriented representation method; lower-level EDA tools; synthesizable RTL descriptions; system-level design environment; system-level specification; verified specification; B-ISDN; Clocks; Data structures; Electronic design automation and methodology; Formal specifications; Hardware design languages; Network synthesis; Optical fiber networks; System-level design; Timing;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655962
