Hierarchical LVS based on hierarchy rebuilding

Author

Kim, Wonjong ; Shin, Hyunchul

Author_Institution

Dept. of Electron. Eng., Hanyang Univ., Ansan, South Korea

fYear

1998

fDate

10-13 Feb 1998

Firstpage

379

Lastpage

384

Abstract

A new hierarchical layout vs. schematic (LVS) verification system has been developed for layout verification. It compares a hierarchical schematic netlist and a flattened layout netlist. The schematic hierarchy is restructured for consistent hierarchical matching and then the same hierarchy is built from the layout netlist. For efficiency, simple gates are found by using a fast rule-based pattern matching algorithm. Each subcircuit is found from the layout by using a modified SubGemini algorithm in bottom-up fashion. Experimental results show that our hierarchical netlist comparison technique is effective and efficient in CPU time and in memory usage

Keywords

circuit layout CAD; pattern matching; fast rule-based pattern matching; flattened layout netlist; hierarchical layout; hierarchical schematic netlist; layout verification; schematic; simple gates; verification system; Central Processing Unit; Circuit simulation; Circuit testing; Computational modeling; Heuristic algorithms; Manufacturing; Partitioning algorithms; Pattern matching; Polynomials; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-4425-1

Type

conf

DOI

10.1109/ASPDAC.1998.669504

Filename

669504