Reinvestigation of dot formation mechanisms in silicon nanowire channel single-electron/hole transistors operating at room temperature

Author

Suzuki, Ryota ; Nozue, Motoki ; Saraya, Takuya ; Hiramoto, Toshiro

Author_Institution

Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan

fYear

2012

fDate

10-11 June 2012

Firstpage

1

Lastpage

2

Abstract

Dot formation mechanisms of single-electron transistors (SETs) and single-hole transistors (SHTs) are reinvestigated. “Shared channel” SET/SHTs in form of nanowire (NW) channel FETs are fabricated and characterized. It is suggested that, in addition to quantum confinement effect (QCE), the positive charges create parasitic dots in SHT channels resulting in multiple-dot SHTs. It is concluded that a <;110>; SET is the best structure to obtain room temperature (RT) operating single-dot device with high yield.

Keywords

elemental semiconductors; field effect transistors; nanowires; silicon; single electron transistors; FET; Si; dot formation mechanisms; multiple-dot SHT; parasitic dots; quantum confinement effect; shared channel SET-SHT; silicon nanowire channel single-electron transistors; silicon nanowire channel single-hole transistors; single-dot device; temperature 293 K to 298 K; FETs; Fabrication; Logic gates; Modulation; Oscillators; Shape; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Nanoelectronics Workshop (SNW), 2012 IEEE

Conference_Location

Honolulu, HI

ISSN

2161-4636

Print_ISBN

978-1-4673-0996-7

Electronic_ISBN

2161-4636

Type

conf

DOI

10.1109/SNW.2012.6243337

Filename

6243337