Application of multirate digital filter banks to wideband all-digital phase locked loops design

A new class of architecture for all-digital phase locked loops (DPLLS) is presented. This architecture, referred to as parallel DPLL (PDPLL), is based on employing multirate digital filter banks (DFBs) to track signals with a lower processing rate than the Nyquist rate, without reducing the input (Nyquist) bandwidth. The PDPLL basically trades complexity versus hardware processing speed by introducing parallel processing in the receiver. A reduced complexity DFB that is ideal for implementation of the PDPLL is introduced. It is demonstrated that the PDPLL performance is identical to that of a DPLL for both steady state and transient behavior. Various Doppler characteristics are used to compare the performance of the DPLL with the PDPLL