DocumentCode
2653357
Title
The size optimize of DCVSPG logic
Author
Xie, Yuanbin ; Pan, Weitao ; Ma, Peijun ; Hao, Vue
Author_Institution
Key Lab. of the Minist. of Educ. for Wide Band-Gap Semicond. Mater. & Devices, Xidian Univ., Xi´´an, China
fYear
2009
fDate
20-23 Oct. 2009
Firstpage
1051
Lastpage
1054
Abstract
In this paper, a simple delay model for manual analysis of DCVSPG logic is built to evaluate the delay of the circuit. The delay obtained by the model is very close to that obtained by HSPICE Also the model can be used to optimize the size of NMOS transistors in DCVSPG logic under specific constraints. At last, the technique how to use this model is displayed.
Keywords
circuit optimisation; delay circuits; integrated circuit design; integrated logic circuits; DCVSPG logic; NMOS transistors; circuit delay; delay model; Arithmetic; CMOS logic circuits; Capacitance; Delay; Logic circuits; Logic design; MOS devices; MOSFETs; Switches; Voltage; DCVSPG logic; Elmore delay; RC model;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location
Changsha, Hunan
Print_ISBN
978-1-4244-3868-6
Electronic_ISBN
978-1-4244-3870-9
Type
conf
DOI
10.1109/ASICON.2009.5351506
Filename
5351506
Link To Document