DocumentCode :
2654262
Title :
High performance and low latency mapping for neural network into network on chip architecture
Author :
Dong, Yiping ; Wang, Yang ; Lin, Zhen ; Watanabe, Takahiro
Author_Institution :
Grad. Sch. of Inf., Waseda Univ., Kitakyushu, Japan
fYear :
2009
fDate :
20-23 Oct. 2009
Firstpage :
891
Lastpage :
894
Abstract :
Various hardware implementations of neural networks have been studied well in recent years. We have already proposed a hardware implementation method for neural network with a network on chip (NoC) architecture. A mapping of a neural network on NoC should be tuned to achieve high performance whenever neural network application is changed, so that different mapping methods are needed every time and tedious or burdensome works are required. In this paper, we propose a general mapping strategy based on three rules. The mapping method with this strategy can implement different neural networks applications with NoC architecture. The simulation results show that the proposed method makes the system low latency and high performance.
Keywords :
network-on-chip; neural nets; NoC architecture; general mapping strategy; network on chip architecture; neural network mapping; Artificial neural networks; Computer architecture; Costs; Delay; Educational technology; Network-on-a-chip; Neural network hardware; Neural networks; Neurons; Table lookup; Artificial Neural Network (ANN); Network on Chip (NoC); NoC architecture; hardware implementation; mapping method;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
Type :
conf
DOI :
10.1109/ASICON.2009.5351550
Filename :
5351550
Link To Document :
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