Title :
Single-phase adiabatic flip-flops and sequential circuits with power-gating scheme
Author :
Ni, Haiyan ; Hu, Jianping
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China
Abstract :
This paper presents the implementations of adiabatic flip-flops and sequential circuits using single-phase power-clock with power-gating scheme. All circuits are realized by using the improved single-phase CAL (clocked adiabatic logic) technology. A power-gating scheme for the improved CAL circuits is used to reduce energy dissipation in sleep mode. All circuits are implemented using Chartered 0.35 ¿m CMOS technology, and full-custom layouts are drawn. Based on the HSPICE simulations with post-layout extracted parasitic, the single-phase adiabatic sequential circuits with the power-gating scheme attain large energy savings over a wide range of frequencies, as compared with conventional CAL circuits and improved CAL circuits.
Keywords :
CMOS logic circuits; SPICE; circuit layout; clocks; flip-flops; logic design; low-power electronics; sequential circuits; CAL circuit; CMOS technology; HSPICE simulation; clocked adiabatic logic; energy dissipation; full-custom layout; power-gating scheme; sequential circuit; single-phase CAL; single-phase adiabatic flip-flops; single-phase power-clock; size 0.35 mum; sleep mode; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit testing; Clocks; Energy dissipation; Flip-flops; Logic circuits; MOSFETs; Sequential circuits; Adiabatic logic; Low-power design; Powergating; Single-phase flip-flop;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351555
