DocumentCode
2655832
Title
Quality estimation of test vectors and functional validation procedures based on fault and error models
Author
Riesgo, T. ; Torroja, Y. ; de la Torre, E. ; Uceda, J.
Author_Institution
Div. de Ingenieria Electron., Univ. Politecnica de Madrid, Spain
fYear
1998
fDate
23-26 Feb 1998
Firstpage
955
Lastpage
956
Abstract
This paper presents a method to estimate the quality of a set of test vectors and the validation procedures from pre-synthesised descriptions in VHDL. The method is based on the definition of fault models, for test features evaluation, and error models, for quality validation estimation
Keywords
digital simulation; fault diagnosis; hardware description languages; integrated circuit testing; logic testing; VHDL; error models; fault models; functional validation procedures; quality estimation; test vectors; validation estimation; Circuit faults; Circuit simulation; Environmental economics; Formal verification; Integrated circuit synthesis; Logic testing; Performance evaluation; Process design; Read only memory; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655986
Filename
655986
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