Title :
A defect and fault tolerant design of WSI static RAM modules
Author_Institution :
NTT Commun. & Inf. Process. Labs., Kanagawa, Japan
Abstract :
Advanced redundancy configurations of static RAM modules based on word duplication and selection by horizontal parity checking (WDSH), as well as based on error correction by horizontal and vertical parity checking (ECHV), are proposed for enhancement of defect and fault tolerance capability of WSIs. The following additional redundancy technologies are applied to them: word selection by automatic access error checking, pair unit replacement are for WDSH-based configurations using multiple RAM units, and two-level hierarchical redundancy is for ECHV-based ones. Performance estimation using a 1.5-micron 128 K-bit CMOS static RAM module model indicates that a remarkably higher degree of effective active area reduction, in respect to defect and fault occurrence, can be attained by an optimum WDSH-based configuration than by a general triplication-based redundancy configuration
Keywords :
CMOS integrated circuits; VLSI; fault tolerant computing; integrated circuit technology; integrated memory circuits; random-access storage; redundancy; CMOS; WSI static RAM modules; active area reduction; defect tolerant design; error correction; fault tolerant design; horizontal and vertical parity checking; multiple RAM units; pair unit replacement; redundancy configurations; redundancy technologies; selection by horizontal parity checking; two-level hierarchical redundancy; word duplication; word selection by automatic access error checking; CMOS technology; Circuit faults; Error correction; Fault tolerance; Information processing; Laboratories; Logic circuits; Random access memory; Redundancy; Semiconductor device modeling;
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
DOI :
10.1109/ICWSI.1990.63903
