DocumentCode :
2656841
Title :
Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate
Author :
Cai, Jin ; Kumar, Mahender ; Steigerwalt, Michael ; Ho, Herbert ; Schonenberg, Kathryn ; Stein, Kenneth ; Chen, Huajie ; Jenkins, Keith ; Ouyang, Qiqing ; Oldiges, Philip ; Ning, Tak
Author_Institution :
Res. Div., T.J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
2003
fDate :
28-30 Sept. 2003
Firstpage :
215
Lastpage :
218
Abstract :
We present a comprehensive study of the DC, RF and circuit performance of vertical SiGe-base npn bipolar transistors on 120nm SOI. It includes the sensitivity of device performance to collector doping NC, layout, and SOI substrate bias. At large positive substrate bias, measured peak fT, fMAX and ECL ring oscillator speed for nominal 180nm devices are 60GHz, 57GHz and 20psec for NC=1.5×1017/cm3 respectively, and 71GHz, 54GHz and 18psec for NC=4.8×1017/cm3 respectively. Projected fT for a scaled 100nm device on 55nm SOI approaches 200GHz.
Keywords :
bipolar transistors; semiconductor device testing; silicon compounds; silicon-on-insulator; 100 nm; 120 nm; 18 psec; 180 nm; 20 psec; 200 GHz; 54 GHz; 55 nm; 57 GHz; 60 GHz; 71 GHz; CMOS-compatible SOI substrate; DC circuits; ECL ring oscillator speed; RF circuits; SOI substrate bias; SiGe; collector doping; emitter coupled logic; npn bipolar transistors; silicon-on-insulator; vertical base bipolar transistors; Bipolar transistors; Semiconductor device testing; Silicon compounds; Silicon on insulator technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 2003. Proceedings of the
ISSN :
1088-9299
Print_ISBN :
0-7803-7800-8
Type :
conf
DOI :
10.1109/BIPOL.2003.1274969
Filename :
1274969
Link To Document :
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