DocumentCode
2656944
Title
Write/erase speed modeling of scaled SONOS and TANOS nonvolatile semiconductor memory (NVSM) devices
Author
Wang, Gan ; Eichenlaub, Nathan ; Jin, Zhian ; Zhang, Yanli ; White, Marvin H.
Author_Institution
Lehigh Univ., Sherman
fYear
2007
fDate
12-14 Dec. 2007
Firstpage
1
Lastpage
2
Abstract
We have developed a pulse response model of write/erase operations for SONOS NVSMs. In this model, we consider the major charge transport mechanisms are band to band tunneling and trap-assisted tunneling. The storage charges in the nitride are treated as a sheet charge at the center of the nitride films. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data.
Keywords
random-access storage; semiconductor device models; silicon compounds; NVSM; SONOS; TANOS; band to band tunneling; major charge transport; nonvolatile semiconductor memory; numerical method; pulse response model; speed modeling; threshold voltages; trap assisted tunneling; write/erase operations; Charge carrier processes; Educational institutions; Electrodes; Electron traps; Gallium nitride; Nonvolatile memory; SONOS devices; Semiconductor memory; Threshold voltage; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Device Research Symposium, 2007 International
Conference_Location
College Park, MD
Print_ISBN
978-1-4244-1892-3
Electronic_ISBN
978-1-4244-1892-3
Type
conf
DOI
10.1109/ISDRS.2007.4422271
Filename
4422271
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