• DocumentCode
    2658026
  • Title

    Automatic hardware-efficient SoC integration by QoS network on chip

  • Author

    Bolotin, Evgeny ; Morgenshtein, Arkadiy ; Cidon, Israel ; Ginosar, Ran ; Kolodny, Avinoam

  • Author_Institution
    Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
  • fYear
    2004
  • fDate
    13-15 Dec. 2004
  • Firstpage
    479
  • Lastpage
    482
  • Abstract
    Efficient module integration in systems on chip (SoC) is a great challenge. We present a novel automated network on chip (NoC) centric integration method for large and complex SoCs. A quality of service NoC (QNoC) architecture and its design considerations are presented. Then, we describe a chain of design automation tools that allows fast and hardware-efficient SoC integration using the QNoC paradigm. The tool-chain receives a list of system modules and their inter-module communication requirements and results in complete system hardware and verification models for faster SoC fabrication and easier verification.
  • Keywords
    formal verification; integrated circuit interconnections; logic CAD; multiprocessor interconnection networks; network routing; quality of service; system-on-chip; CAD tools; NoC; QNoC; QoS network on chip; SoC verification; automatic hardware-efficient SoC integration; design automation tools; point-to-point link interconnected routers; system inter-module communication; verification models; wormhole packet routing; Bandwidth; Buffer storage; Communication system control; Delay; Network-on-a-chip; Payloads; Radio access networks; Routing; Telecommunication traffic; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on
  • Print_ISBN
    0-7803-8715-5
  • Type

    conf

  • DOI
    10.1109/ICECS.2004.1399722
  • Filename
    1399722