Title :
High performance cryptographic engine PANAMA: hardware implementation
Author :
Selimis, G. ; Kitsos, P. ; Koufopavlou, O.
Author_Institution :
Electr. & Comput. Eng. Dept., Patras Univ., Greece
Abstract :
A hardware implementation of a dual operation cryptographic engine, PANAMA, is presented. The implementation of the PANAMA algorithm can be used both as a hash function and a stream cipher. A basic characteristic of PANAMA is a high degree of parallelism which has, as a result, high rates for the overall system throughput. Another profit of PANAMA is that just one architecture supports two cryptographic operations - encryption/decryption and data hashing. The proposed system operates at 96.5 MHz frequency with a maximum data rate of 24.7 Gbps. The proposed system outperforms previous hash function and stream cipher implementations in terms of performance. Additional techniques can increase the achieved throughput by about 90%.
Keywords :
cryptography; field programmable gate arrays; integrated circuit design; logic design; FPGA synthesis; PANAMA cryptographic engine; data hashing; decryption; dual operation cryptographic engine; encryption; hardware implementation; hash function; stream cipher; Authentication; CMOS technology; Cryptography; Design engineering; Engines; Field programmable gate arrays; Hardware; Switches; Throughput; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on
Print_ISBN :
0-7803-8715-5
DOI :
10.1109/ICECS.2004.1399746
