Ultra low-power DFF based shift registers design for CMOS image sensors applications

Various implementations of D-flip-flops (DFF) for shift register designs in CMOS image sensors are proposed. Driven by requirements of low-area and low-power dissipation, the presented FF allow implementation of power-efficient shift registers, used for signal readout control and windows of interest definition in CMOS image sensors and are optimized for operation at low frequencies. Power dissipation of the presented DFF is significantly reduced by leakage control using the stack effect. A variety of DFF and a shift-register, using the stacking effect approach, have been implemented in 0.18 μm standard CMOS technology to compare the proposed DFF and shift-register structures with existing alternatives, showing an up to 63 % reduction in power dissipation of a shift-register at 30 Hz frequency. Operation of the proposed circuits is discussed and simulation results are reported.