Title :
A lay-out level comparison of RNS and BNS systolic architectures for complex digital filtering
Author :
Krishnan, Ramasamy
Author_Institution :
Boeing Electron. High Technol. Center, Seattle, WA, USA
Abstract :
Algorithms are developed to compute the number of active devices for residue number system (RNS) and binary number system (BNS) signal processing architectures. The precharged CMOS technology is used in order to build the filter architecture. The ROM lookup table and two´s complement multiplier are used as the computational cells in the RNS and BNS, respectively. A direct implementation transversal systolic filter architecture is considered in RNS and BNS algorithms
Keywords :
CMOS integrated circuits; circuit layout CAD; computerised signal processing; digital arithmetic; digital filters; digital signal processing chips; systolic arrays; table lookup; BNS; RNS; ROM lookup table; binary number system; complex digital filtering; direct implementation; lay-out level comparison; precharged CMOS technology; residue number system; signal processing architectures; systolic architectures; transversal systolic filter architecture; two´s complement multiplier; Arithmetic; CMOS technology; Circuits; Computer architecture; Digital filters; Filtering; Finite impulse response filter; Signal processing; Signal processing algorithms; Transversal filters;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112449
