Title :
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges
Author :
Moriwaki, S. ; Yamamoto, Y. ; Kawasumi, A. ; Suzuki, T. ; Miyano, S. ; Sakurai, T. ; Shinohara, H.
Author_Institution :
Semicond. Technol. Acad. Res. Center (STARC), Yokohama, Japan
Abstract :
1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.
Keywords :
SRAM chips; SRAM; bit line swing; charge collector circuits; nonselected bit line charges; nonselected columns; power consumption; size 40 nm; wasted power sources; Power demand; Power dissipation; Power measurement; Random access memory; Transistors; Very large scale integration; Voltage measurement; 6T; SRAM; charge-share;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243789
