Investigation of effectiveness of split image plane for ESD immunity in system level

In recently years, high speed digital circuit equipment and products with electrostatic discharge (ESD) issues have become crucial due to tighter rise time and smaller geometry spacing. A typical ESD trouble shooting case is discussed involving a personal computer system followed with plain analysis to confirm the ESD interference path in a complex system. Further analysis studies several printed circuit board (PCB) structure traces relative to crosstalk. The target ESD immunity is then increased up from ±4 kV to ±6 kV contact discharge for the margin design to ensure the improved effect using a novel technique in this evaluated system. The simulation result is verified to be in good agreement with the measurement result.