Title :
A discrete event systems approach to online testing of digital VLSI circuits
Author :
Biswas, Santosh ; Mukhopadhyay, Siddhartha ; Patra, Amit
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Kharagpur, India
Abstract :
The current work is focused towards the development of algorithms and CAD tools for the design of digital circuits with on line testing capability. The methodology is based on the theory of fault detection and diagnosis of discrete event systems. The paper deals with optimization of the algorithms of fault detection to alleviate the problem of state explosion based on symbolic techniques like "ordered binary decision diagrams" and "abstraction". With the help of these algorithms a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capabilities and can handle generic digital circuits with cell count as high as 15,000 and about 2500 states. Further, this methodology provides the designer with a wide range of tradeoffs in detector design: fault coverage and detection latency vs. area and power overhead.
Keywords :
VLSI; binary decision diagrams; circuit CAD; digital circuits; discrete event systems; fault diagnosis; finite state machines; optimisation; testing; CAD tools; detection latency; digital VLSI circuit; discrete event system; fault coverage; fault detection; fault diagnosis; finite state machine; online testing; ordered binary decision diagram; Algorithm design and analysis; Circuit testing; Design automation; Digital circuits; Discrete event systems; Electrical fault detection; Fault detection; Fault diagnosis; System testing; Very large scale integration;
Conference_Titel :
Systems, Man and Cybernetics, 2004 IEEE International Conference on
Print_ISBN :
0-7803-8566-7
DOI :
10.1109/ICSMC.2004.1399876