Title :
x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression
Author :
Fujii, Hiroki ; Miyaji, Kousuke ; Johguchi, Koh ; Higuchi, Kazuhide ; Sun, Chao ; Takeuchi, Ken
Author_Institution :
Dept. Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan
Abstract :
A 3D through-silicon-via (TSV) -integrated hybrid ReRAM/multi-level-cell (MLC) NAND solid-state drives´ (SSDs´) architecture is proposed for PC, server and smart phone applications. NAND-like interface (I/F) and sector-access overwrite policy are proposed for the ReRAM. Furthermore, intelligent data management algorithms are proposed. The proposed algorithms suppress data fragmentation and excess usage of the MLC NAND by storing hot data in the ReRAM. As a result, 11 times performance increase, 6.9 times endurance enhancement and 93% write energy reduction are achieved compared with the conventional MLC NAND SSD. Both ReRAM write and read latency should be less than 3μs to obtain these improvements. The required endurance for ReRAM is 105. 3D TSV interconnects reduce the energy consumption by 68%.
Keywords :
NAND circuits; integrated circuit interconnections; random-access storage; three-dimensional integrated circuits; 3D TSV interconnects; 3D TSV-integrated hybrid ReRAM; 3D through-silicon-via; MLC NAND SSD; NAND-like interface; PC; data fragmentation suppression; endurance enhancement; energy consumption; intelligent data management algorithms; multilevel-cell NAND solid-state drive architecture; read latency; sector-access overwrite policy; server; smart phone; write energy reduction; Current measurement; Flash memory; Heuristic algorithms; Random access memory; Servers; Through-silicon vias; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243826