Title :
1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS
Author :
Chung, Sang-Hye ; Kim, Lee-Sup
Author_Institution :
KAIST, Daejeon, South Korea
Abstract :
This paper presents a data jitter mixing forwarded-clock receiver which is robust against power supply induced jitter (PSIJ) and overcomes 1.92ns latency mismatch between data and clock. The forwarded-clock architecture has a tradeoff between the number of clock channels and the achievable data rate due to the lack of the jitter correlation between data and clock. Moreover, PSIJ due to a long clock distribution network and an injection-locked oscillator reduces the jitter correlation further. The proposed receiver eases this tradeoff, and also increases the jitter correlation reduced by PSIJ. The test chip achieves 9.6Gb/s with 1.22mW/Gb/s and occupies only 0.017mm2 in 65nm CMOS.
Keywords :
CMOS digital integrated circuits; clock distribution networks; injection locked oscillators; jitter; receivers; PSIJ; bit rate 9.6 Gbit/s; data jitter mixing forwarded-clock receiver; injection-locked oscillator; jitter correlation; latency mismatch; long clock distribution network; power noise; power supply induced jitter; size 65 nm; time 1.92 ns; Bit error rate; Calibration; Clocks; Correlation; Jitter; Receivers; Synchronization; Source synchronous link; data jitter mixing; injection-locked oscillator; receiver;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243831