Title :
Complementary 25 V LDMOS for analog applications based on 0.6 μm BiCMOS technology
Author :
Nakamura, Kazutoshi ; Kawaguchi, Yusuke ; Karouji, Kumiko ; Watanabe, Kiminori ; Yamaguchi, Yoshihiro ; Nakagawa, Akio
Author_Institution :
Discrete Semicond. Div., Toshiba Corp. Semicond. Co., Kawasaki, Japan
Abstract :
A complementary 25 V LDMOS for analog applications based on 0.6 μm BiCMOS technology has been developed. The n-channel LDMOS has two-step shallow n-implant layers which achieve low on-resistance and large safe operation area (SOA). The n-channel and p-channel LDMOS achieve high on-state breakdown voltages of 33 V and 50 V, respectively, for a gate voltage of 5.0 V. The values of specific on-resistance are 27.5 mΩ·mm2 for n-channel and 111 mΩ·mm2 for p-channel LDMOS
Keywords :
BiCMOS analogue integrated circuits; doping profiles; electric resistance; ion implantation; power MOSFET; semiconductor device breakdown; semiconductor device measurement; 0.6 micron; 25 V; 33 V; 5 V; 50 V; BiCMOS technology; SOA; analog applications; complementary LDMOSFET; gate voltage; n-channel LDMOS; on-resistance; on-state breakdown voltage; p-channel LDMOS; safe operation area; specific on-resistance; two-step shallow n-implant layers; Application software; BiCMOS integrated circuits; Breakdown voltage; Degradation; Electrons; Facsimile; Implants; Laboratories; Large scale integration; MOSFETs;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 2000. Proceedings of the 2000
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-6384-1
DOI :
10.1109/BIPOL.2000.886181
