Title :
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier
Author :
Kim, KwangSeok ; Kim, YoungHwa ; Yu, WonSik ; Cho, SeongHwan
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
Abstract :
This paper presents a time-to-digital converter (TDC) using a novel pulse-train time amplifier. The proposed TDC exploits repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. Using this circuit, a 7-bit two-step time-to-digital converter is implemented. The prototype chip fabricated in 65nm CMOS process achieves 3.75ps of time resolution at 200Msps while consuming 3.6mW and occupying 0.02mm2.
Keywords :
CMOS analogue integrated circuits; amplification; amplifiers; time-digital conversion; CMOS process; TDC; calibration-free; gated delay-lines; power 3.6 mW; programmable time amplification; prototype chip; pulse-train time amplifier; quantization; resolution two-step time-to-digital converter; size 65 nm; time 3.75 ps; word length 7 bit; CMOS integrated circuits; Calibration; Delay; Linearity; Logic gates; Quantization; Very large scale integration; PLL and ADPLL; time amplifier; time-to-digital converter (TDC); two-step architecture;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243855
