Title :
Layout generation algorithm for CMOS analog IC cells
Author :
Liang, Tsien ; Syrzycki, Marek
Author_Institution :
Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
Abstract :
This paper presents the development of an algorithm for the placement of transistors in analog IC layout design. The properties and implementation techniques of the algorithm are introduced along with sample layouts produced for a test circuit
Keywords :
CMOS analogue integrated circuits; circuit layout CAD; integrated circuit layout; CMOS analog IC cells; analog IC layout design; layout generation algorithm; test circuit; transistor placement; Algorithm design and analysis; Analog integrated circuits; CMOS analog integrated circuits; CMOS integrated circuits; CMOS technology; Circuit testing; Integrated circuit layout; Integrated circuit noise; Parasitic capacitance; Pattern matching;
Conference_Titel :
Electrical and Computer Engineering, 1998. IEEE Canadian Conference on
Conference_Location :
Waterloo, Ont.
Print_ISBN :
0-7803-4314-X
DOI :
10.1109/CCECE.1998.685581
