DocumentCode :
2663995
Title :
Reducing Test Power for Embedded Memories
Author :
Awad, Ahmed ; Abu-Issa, Abdallatif ; Hamdioui, Said
Author_Institution :
Fac. of Inf. Technol., Birzeit Univ., Ramallah, Palestinian Authority
fYear :
2011
fDate :
3-5 Oct. 2011
Firstpage :
112
Lastpage :
119
Abstract :
With the increased number of embedded memories in mobile devices, minimizing the test power becomes a serious concern, especially when parallel testing is applied. Battery will be lost and the entire System on Chip (SoC) is subjected to be damaged if the peak power exceeds the power constraint. This paper proposes a new scheme to reduce the peak power during embedded SRAMs testing in mobile devices. The scheme is based on (a) grouping different memories into clusters based on their word lengths, and (b)scheduling read and write operations in such a way that the consumed power is minimal. Simulation results of a case-of-study show that up to 60% in the peak power reduction can be achieved, at a cost of only one additional clock cycle test time.
Keywords :
SRAM chips; integrated circuit testing; mobile handsets; system-on-chip; SoC; clock cycle test time; embedded SRAM testing; embedded memories; mobile devices; parallel testing; peak power reduction; power constraint; system on chip; test power; test power reduction; Clocks; Clustering algorithms; Memory management; Random access memory; Switches; System-on-a-chip; Testing; Average power; March Test; Memory BIST; Parallel testing; Peak power; Word oriented SRAM;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on
Conference_Location :
Vancouver, BC
Print_ISBN :
978-1-4577-1713-0
Type :
conf
DOI :
10.1109/DFT.2011.59
Filename :
6104434
Link To Document :
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