Synthesis of regular computational fabrics with ambipolar CNTFET technology

In this paper, we report on a physical design of regular fabrics with ambipolar CNTFET devices. Three medium-grain size cells, built with ambipolar CNTFETs with in-field controllable polarities are evaluated. We designed regular layouts using these cells using 32nm technology rules and we performed technology mapping and routing of a set of benchmark circuits. CNTFET-based cells were then compared with an existent configurable cell of similar grain size, the Actel ACT1 logic brick, simulated with a 32nm MOSFET model. We obtained delays about 2× better than those obtained with ACT1 after normalization to the intrinsic technology delay. After technology mapping and routing steps, we report performances about 8× better in terms of area × normalized delay for the CNTFET-based cells over the Actel ACT1 cell.