Title :
Integrated BiCMOS process and circuit development using SPR
Author :
Ryter, R. ; Zingg, R. ; Hegarty, C. ; Fichtner, W. ; Doering, E.
Author_Institution :
ETH-Zentrum, Zurich, Switzerland
Abstract :
An integrated process development environment is described. Geometry information for process simulation is taken automatically from a commercial layout tool, and process step information exists in a high-level language databank. Doping information can be read by a device simulator, permitting SPICE (simulation program with IC emphasis)-like circuit simulation. This environment is presented in a BiCMOS development context
Keywords :
BiCMOS integrated circuits; SPICE; circuit analysis computing; circuit layout CAD; circuit optimisation; integrated circuit layout; masks; semiconductor process modelling; BiCMOS development; SPICE-like simulation; circuit development; commercial layout tool; high-level language databank; integrated process development environment; mask generating; process simulation; process step information; semiconductor process representation; BiCMOS integrated circuits; CMOS process; CMOS technology; Circuit simulation; Computer aided manufacturing; Equations; Fabrication; Laboratories; Microelectronics; Solid modeling;
Conference_Titel :
Electronic Manufacturing Technology Symposium, 1993, Fifteenth IEEE/CHMT International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-1424-7
DOI :
10.1109/IEMT.1993.398216
