A distributed kernel for VHDL simulation

The authors describe a technique for simulating large-scale VHDL (BHSIC hardware description language) models on a distributed computer composed of independent processing units communicating via messages. The distributed VHDL simulation system consists of a scalable kernel which can support a large simulation composed of many concurrent VHDL processes. Each concurrent VHDL statement maps into a logical process in the simulated system. The kernel provides model-independent support functions that handle signal propagation and process activation in a distributed environment. The synchronization between individual logical processes in the kernel is handled using the Chandy-Misra null message protocol for distributed simulation. The distributed kernel has been implemented using the University of Virginia´s Spectrum portable simulation testbed, and runs on the Intel iPSC/2 Hypercube computer. Several test circuits have been simulated to show the feasibility of simulating VHDL models in a distributed system. The test circuits include structural models of both combinational logic and sequential logic