Improved MPSoC co-design methodology for stream oriented processing applications

This paper presents a top-down co-design flow, based on the streams-C compiler and open processor architectures to simplify and accelerate the design cycle time of MPSoC platforms for stream processing applications. An application is first modeled as a collection of HW and SW Communicating Sequential Processes (CSP) described in C-code and targeted at stream-oriented FPGA applications. Then, it is synthesized as a custom MPSoC architecture consisting of HW and SW components interconnected with a custom hierarchical communication bus architecture. The latter optimizes resource usage, with dedicated HW/SW interfaces, to reduce area in the FPGA. The effectiveness of our methodology is demonstrated in two real-time image processing applications.