DocumentCode :
2668918
Title :
A new synchronization policy between PSL checkers and SystemC designs at transaction level
Author :
Lahbib, Younes ; Ghrab, Mohamed-Arafet ; Hechkel, Maher ; Ghenassia, Frank ; Tourki, Rached
Author_Institution :
Electron. & Microelectron. Lab., ST Microelectron., Monastir
fYear :
2006
fDate :
5-7 Sept. 2006
Firstpage :
85
Lastpage :
90
Abstract :
The authors present a technique to synchronize between PSL (property specification language) checkers and SystemC IPs at the highest abstraction level of the ST Microelectronics system flow: transaction level modeling (TLM). A new assertion-based verification approach is proposed. It consists of a runtime simulation of the system-on-chip (SoC) under verification with PSL checkers. In this approach, the PSL checkers that represent the system specification are converted into C++ and therefore into a SystemC-TLM modules, which refer to us as TLM checkers. However, when integrating TLM checkers with SystemC models of SoC, the traditional clock-based synchronization at register transfer level and lower could not be applied. In fact, at the TLM abstraction level, the modeling rules forbid the use of a hardware clock. A new synchronization policy should be then proposed, hence the aim of this paper
Keywords :
C++ language; formal specification; formal verification; synchronisation; system-on-chip; ABV; C++ language; PSL checkers; SystemC IP; SystemC-TLM; assertion based verification; property specification language; register transfer level; system-on-chip; transaction level modeling; Clocks; Computer bugs; Consumer electronics; Hardware; Laboratories; Microelectronics; Object oriented modeling; Runtime; Specification languages; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on
Conference_Location :
Tunis
Print_ISBN :
0-7803-9726-6
Type :
conf
DOI :
10.1109/DTIS.2006.1708698
Filename :
1708698
Link To Document :
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