Title :
A high performance FPGA implementation of DES
Author :
McLoone, Máire ; McCanny, John V.
Author_Institution :
Sch. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK
Abstract :
FPGAs have proven to be very effective and efficient devices on which to implement encryption algorithms. They perform at much faster data-rates and provide better security than equivalent software implementations. They also provide more flexibility than ASIC implementations. This paper presents a high performance silicon intellectual property (IP) core for the data encryption standard (DES) encryption algorithm. The 16-stage pipelined DES design runs at an encryption rate of 3.87 Gbits/s using Xilinx Virtex FPGA technology making this the fastest single-chip DES FPGA implementation reported to date. This result is a factor 28 times faster than software implementations
Keywords :
code standards; cryptography; field programmable gate arrays; industrial property; pipeline processing; telecommunication standards; 3.87 Gbit/s; DES encryption algorithm; Xilinx Virtex FPGA technology; data encryption standard; encryption algorithms; encryption rate; high performance FPGA implementation; pipelined DES design; security; silicon intellectual property core; single-chip DES FPGA; Application specific integrated circuits; CMOS technology; Cryptography; Data security; Dynamic programming; Field programmable gate arrays; Intellectual property; Laboratories; Protocols; Throughput;
Conference_Titel :
Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-6488-0
DOI :
10.1109/SIPS.2000.886736
